IBM, in collaboration with Samsung and GlobalFoundries, has unveiled the world’s first 5nm silicon chip. Besides the usual improvement in power, performance and density by moving to smaller transistors, the 5nm IBM chip is notable for being one of the first to use horizontal gate-all-around (GAA) transistors, and the first true using extreme ultraviolet (EUV) lithography.
GAAFETs are the next evolution of tri-gate finFETs: finFETs, currently used for most 22nm and below chip designs, are likely to run out around 7nm; GAAFETs can go all the way down to 3nm, especially when combined with EUV. No one really knows what comes after 3nm.
2D, 3D and back to 2D
For a long time, transistors were usually manufactured by depositing layers of different materials on top of each other. As these planar 2D transistors got shorter and shorter (ie more transistors in the same space), it became more and more difficult to make transistors that really perform well (ie fast switching, low leakage, reliable). Eventually, the channel became so small that the handful of remaining silicon atoms couldn’t carry the electricity across the device fast enough.
FinFETs solve this problem by going into the third dimension: instead of the channel being a small 2D piece of silicon, a 3D fin protrudes from the substrate, allowing for a much larger volume of silicon. However, transistors are still getting smaller and fins are getting thinner. Now chipmakers have to use a different type of transistor that offers yet another delay in execution.
Enter GAAFETs, which are kind of 2D, but they build on the expertise, machines and techniques that were needed for finFETs. There are a few ways to build GAAFETs, but in this case IBM/Samsung/GloFo are talking about horizontal devices. The easiest way to think of these lateral GAAFETs is to take a finFET and rotate it 90 degrees. So instead of the channel being a vertical fin, the channel becomes a horizontal fin – or put another way, the fin is now a silicon nanowire (or nanosheet, depending on the width) strung between the source and drain.
In the case of IBM’s GAAFET, there are actually three stacked nanosheets running between the source and the drain, with the gate (the bit that turns the channel on and off) filling in all the gaps. As a result, there is a relatively large volume of gate and channel material – making the GAAFET reliable, powerful and better suited to downsizing even further.
In terms of manufacturing, GAAFETs are particularly fascinating. Basically you lay down a number of alternating stacks of silicon and silicon-germanium (SiGe). Then you gently remove the SiGe with a new process called atomic layer etching (probably with an Applied Materials Selectra machine), creating gaps between each of the silicon layers, which are now technically nanosheets. Finally, without letting those nanosheets hang, fill those gaps with a high-κ gate metal. Filling in the gaps isn’t easy, though IBM has seemingly succeeded with atomic layer deposition (ALD) and the right chemistry.
A major benefit of IBM’s 5nm GAAFETs is a significant reduction in pattern complexity. Since we passed the 28nm node, chips have become increasingly expensive to manufacture, due to the added complexity of fabricating ever-smaller features at ever-increasing densities. Patterning is the multi-stage process in which the layout of the chip, which determines where the nanosheets and other components will ultimately be built, is etched using a lithographic process. As features become smaller and more complex, more pattern stages are required, driving up the cost and time of producing each wafer.
Huiming Bu, head of silicon devices at IBM Research, says this 5nm chip marks the first time extreme ultraviolet (EUV) lithography has been used for front-end-of-line patterns. EUV has a much narrower wavelength (13.5 nm) than current immersion lithography machines (193 nm), which in turn can reduce the number of patterning stages. EUV has been waiting in the wings for about 10 years now, always just a few months away from commercial viability. This is the best sign yet that ASML’s EUV technology is finally ready for primetime.
So, how good are GAAFETs?
IBM says that, compared to commercial 10nm chips (presumably Samsung’s 10nm process), the new 5nm technology offers a 40 percent performance boost at the same power, or a 75 percent reduction in power consumption at the same performance. Density is also skyrocketing, with IBM claiming it can squeeze up to 30 billion transistors onto a 50 square millimeter chip (about the size of a fingernail), versus 20 billion transistors on a similarly sized 7nm chip.
However, GAAFETs have not necessarily sewn the 5nm node. As always in the semiconductor industry, chipmakers prefer to modify existing fabrication processes and transistor designs, rather than spend billions deploying new, immature technology. Current silicon-germanium FinFETs will likely take us to 7nm, and the use of exotic III-V semiconductors could take the finFET one step further to 5nm.
But at some point, it probably won’t be worth the time, cost, and complexity of producing ever-smaller transistors and chips. Someone will realize that there are far greater gains to be made by going 3D properly: stacking dozens of logic dies on top of each other, connected together via through-silicon vias (TSVs). Intel has been looking at chip stacking since 2015 to ease the slow progress to the 10nm node. We may soon see the fruits of that labor; although I doubt they will still be cooled with electronic blood.